The advantages of the three-dimensional-integrated-circuit (3DIC) technique, such as high performance, low power dissipation, low cost, compactness, integration of hetero-generous IC substrates, lead to a potential trend for developing the System on Chip (SoC). Wherein the through-silicon-via (TSV) technique plays a key role of being capable of overcoming the limitations by the IC fabrication process and the low dielectric-constant material, so that the interconnection among the stacked IC chips can be with lower cost and higher performance.
However, misalignment between the TSVs of the stacked IC substrates or conductor bumps between the stacked IC chips happened frequently in the assembly process of the 3DIC, which may lead to potential errors or distortions in the communication of electrical signals. Furthermore, the reliability of the interconnection or assembly of the TSVs is subject to the bumps, which tend to increase the resistance of TSV connection and, even more, to cause cracks or defects of opened circuit. Therefore, it is in need to develop a reliable structure of TSV substrates.